Over the past decade, silicon physical unclonable function (“PUF”) circuits have emerged as highly useful blocks in the design of secure hardware in applications such as identification, authentication and even encryption key generation. In general, PUF circuits derive their randomness from uncontrolled random variation phenomena that occur during the silicon chip manufacturing process. Rather than store a set of random bits, PUF circuits generate these random bits every time they are activated.
Most PUF implementations can do so by amplifying some electrical characteristic (e.g., delay or threshold voltage) from two nominally identical circuit components in the PUF core. For example, delay based PUF circuits, e.g., an arbiter type or ring oscillator type generate their random bits by amplifying a difference in delays of two nominally identical delay paths. Bi-stable element based PUF circuits, e.g., based on static random access memory (SRAM) or sense amplifier technology generate their random bits by amplifying differences in strengths of two or more transistors using a positive feedback structure (e.g., a cross-coupled inverter pair).
These electrical differences, especially when small, can flip a polarity in conditions involving environmental variations, e.g., voltage and temperature changes, in the presence of ambient noise, or over aging, resulting in some bits of the raw PUF circuit response being unreliable. Previous hardware studies have shown that for some designs more than 25% of the PUF circuit response bits may be unreliable across environmental variations. Since differences of larger magnitude require larger variations to flip polarity, larger electrical differences generally result in more reliable PUF circuits. Although some applications, such as identification and authentication, can be designed to tolerate a few errors in the response without significant loss of security, many applications can benefit from more reliable PUF circuits, and applications such as key generation require the PUF circuit response to be perfectly reliable.
The conventional methods to improve PUF circuit reliability use powerful error correction codes (ECC) to correct the raw response from the PUF circuit core. Unfortunately, these ECC blocks generally have significant VLSI overheads that can quickly scale up as the number of bits of correction increases.
Alternate techniques can increase a reliability of the PUF core and thus significantly reduce a strength (and complexity) of the ECC used. One method of increasing the reliability of the PUF core is to use normally detrimental integrated circuit (IC) aging effects to reinforce a desired (or “golden”) response of the PUF by permanently altering the PUF circuit characteristics such that the difference in the electrical characteristic is increased in magnitude, and hence making the PUF more reliable.
Previous work used the IC aging phenomena of negative bias temperature instability (NBTI) to improve reliability of an SRAM circuit by approximately 40%. Despite its efficacy in increasing the SRAM circuit reliability, NBTI-based response reinforcement requires long baking times (e.g., greater than 20 hours) that are incompatible with an industrial high-volume-production manufacture and test flow.
Further, the high temperatures needed for NBTI-based reinforcement cannot be applied selectively, and thus would detrimentally age all circuits on the chip. Finally, transistor VTH shifts due to NBTI are not permanent, and the transistors can return to near their initial characteristics over time. NBTI can typically achieve a permanent VTH shift (after recovery) of only approximately 10-40 mV in PMOS devices over years of stress (equivalent to over tens of hours of accelerated aging under elevated voltage and temperature).
Therefore, a need exists for techniques and circuits to improve a reliability of a PUF circuit.